Module cortex_m::peripheral
source · Expand description
Core peripherals.
§API
To use (most of) the peripheral API first you must get an instance of the peripheral. All the
core peripherals are modeled as singletons (there can only ever be, at most, one instance of any
one of them at any given point in time) and the only way to get an instance of them is through
the Peripherals::take
method.
let mut peripherals = Peripherals::take().unwrap();
peripherals.DCB.enable_trace();
This method can only be successfully called once – this is why the method returns an
Option
. Subsequent calls to the method will result in a None
value being returned.
let ok = Peripherals::take().unwrap();
let panics = Peripherals::take().unwrap();
A part of the peripheral API doesn’t require access to a peripheral instance. This part of the
API is provided as static methods on the peripheral types. One example is the
DWT::cycle_count
method.
{
let mut peripherals = Peripherals::take().unwrap();
peripherals.DCB.enable_trace();
peripherals.DWT.enable_cycle_counter();
} // all the peripheral singletons are destroyed here
// but this method can be called without a DWT instance
let cyccnt = DWT::cycle_count();
The singleton property can be unsafely bypassed using the ptr
static method which is
available on all the peripheral types. This method is a useful building block for implementing
safe higher level abstractions.
{
let mut peripherals = Peripherals::take().unwrap();
peripherals.DCB.enable_trace();
peripherals.DWT.enable_cycle_counter();
} // all the peripheral singletons are destroyed here
// actually safe because this is an atomic read with no side effects
let cyccnt = unsafe { (*DWT::PTR).cyccnt.read() };
§References
- ARMv7-M Architecture Reference Manual (Issue E.b) - Chapter B3
Modules§
- Cache and branch predictor maintenance operations
- CPUID
- Debug Control Block
- Data Watchpoint and Trace unit
- Flash Patch and Breakpoint unit
- Implementation Control Block
- Instrumentation Trace Macrocell
- Memory Protection Unit
- Nested Vector Interrupt Controller
- System Control Block
- SysTick: System Timer
- Trace Port Interface Unit;
Structs§
- Cache and branch predictor maintenance operations
- CPUID
- Debug Control Block
- Data Watchpoint and Trace unit
- Flash Patch and Breakpoint unit
- Floating Point Unit
- Implementation Control Block.
- Instrumentation Trace Macrocell
- Memory Protection Unit
- Nested Vector Interrupt Controller
- Core peripherals
- Security Attribution Unit
- System Control Block
- SysTick: System Timer
- Trace Port Interface Unit