Struct stm32_metapac::timer::TimAdv

pub struct TimAdv { /* private fields */ }

Advanced-timers

Implementations

impl TimAdv

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn cr1(self) -> Reg<Cr1Gp, RW>

control register 1

pub const fn cr2(self) -> Reg<Cr2Adv, RW>

control register 2

pub const fn smcr(self) -> Reg<Smcr, RW>

slave mode control register

pub const fn dier(self) -> Reg<DierAdv, RW>

DMA/Interrupt enable register

pub const fn sr(self) -> Reg<SrAdv, RW>

status register

pub const fn egr(self) -> Reg<EgrAdv, W>

event generation register

pub const fn ccmr_input(self, n: usize) -> Reg<CcmrInput, RW>

capture/compare mode register 1 (input mode)

pub const fn ccmr_output(self, n: usize) -> Reg<CcmrOutput, RW>

capture/compare mode register 1 (output mode)

pub const fn ccer(self) -> Reg<CcerAdv, RW>

capture/compare enable register

pub const fn cnt(self) -> Reg<Cnt16, RW>

counter

pub const fn psc(self) -> Reg<Psc, RW>

prescaler

pub const fn arr(self) -> Reg<Arr16, RW>

auto-reload register

pub const fn rcr(self) -> Reg<Rcr, RW>

repetition counter register

pub const fn ccr(self, n: usize) -> Reg<Ccr16, RW>

capture/compare register

pub const fn bdtr(self) -> Reg<Bdtr, RW>

break and dead-time register

pub const fn dcr(self) -> Reg<Dcr, RW>

DMA control register

pub const fn dmar(self) -> Reg<Dmar, RW>

DMA address for full transfer

Trait Implementations

impl Clone for TimAdv

fn clone(&self) -> TimAdv

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for TimAdv

fn eq(&self, other: &TimAdv) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for TimAdv

impl Eq for TimAdv

impl Send for TimAdv

impl StructuralPartialEq for TimAdv

impl Sync for TimAdv